Integrated circuits are often formed on a semiconductor substrate such as a silicon wafer or other semiconductive material. In general, layers of various materials which are semiconductive, conductive, or dielectric are used to form the integrated circuits. By way of examples, the various materials are doped, ion implanted, deposited, etched, grown, etc. using various processes. A continuing goal in semiconductor processing is to strive to reduce the size of individual electronic components, thereby enabling smaller and denser integrated circuitry.
One type of integrated circuitry comprises memory. Individual memory cells of such circuitry are densely packed within a memory array area, and have conductive lines extending outwardly there-from to connect with control circuitry outside of the memory array area. One type of layout comprises a memory array area having word lines extending there-across. One example type of memory which may use such layout is a non-volatile memory known as flash. Flash memory is a type of EEPROM (Electrically-Erasable Programmable Read-Only Memory) that may be erased and reprogrammed in blocks. Most personal computers have BIOS stored on a flash memory chip. Further, flash continues to find increasing use in consumer devices such as MP3 players, cell phones, digital cameras, etc.
There is a continuing goal in the fabrication of memory and other integrated circuitry to reduce feature sizes, such as the widths of word lines, to create smaller and denser integrated circuitry. Reduced feature sizes for integrated circuits are related to the techniques used to form those features. For example, photolithography is one technique used to pattern features of integrated circuits. A concept commonly referred to as “pitch” is used to describe the sizes of the features in conjunction with spaces immediately adjacent thereto. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern, thereby including the maximum width of the feature and the space to the next immediately adjacent feature. Due to factors such as optics and light or radiation wave length, photolithography techniques tend to have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction using photolithography.
Pitch multiplication is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. This method forms features narrower than minimum photolithography resolution by, for example, depositing spacer-forming layers that have a lateral thickness that is less than that of the minimum capable photolithographic feature size. The spacer-forming layer is anisotropically etched to form sub-lithographic features, and then the features which were formed at the minimum photolithographic feature size may be etched from the substrate. Using such techniques where pitch is actually halved, the reduction is commonly referred to as pitch “doubling”. More generally, pitch “multiplication” encompasses change in pitch by two or more times, and also of fractional values other than integers. Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reduction of the pitch by that factor.
Photolithographic and other techniques used to pattern an array of repeating features may not form those features at the edges of the array the same as those formed within a more central region away from the array edges. This is due to optical or other effects that result in the edge features patterning differently than the more central features. Existing manners for overcoming these drawbacks are to form the edge features to be larger and/or have greater pitch than the more central region features. Alternately or additionally, dummy features may be formed at the edge(s) of arrays which either do not resolve into underlying substrate material or result in the formation of underlying structures having no circuit function. Regardless, these example prior art techniques for overcoming this problem undesirably consume horizontal substrate area which might otherwise be used in the fabrication of operable circuit components.